1. Technical Field
The present invention relates to an apparatus for data processing in general, and in particular to a binary adder. Still more particularly, the present invention relates to a 6-to-3 carry-save binary adder.
2. Description of the Prior Art
The two most commonly encountered binary adders in digital arithmetic circuit arrangements are carry-propagate adders (CPAs) and carry-save adders (CSAs). CPAs are typically designed to have two data inputs and one output known as a sum. CPAs operate according to well-known principles in which addend bits of the same order are added together, and a carry bit will be transferred to an adjacent higher order bit when required. The final sum is directly derived from a bit-by-bit addition, with an appropriate carry to an adjacent higher order bit and a single bit carry out from the highest order bit position. The ripple carry of a CPA tends to result in slow non-parallel operations because high order bits computations are dependent on the results from low order bits.
CSAs, on the other hand, typically have three data inputs and two outputs. Carry bits in CSAs are accumulated separately from the sum bits of any given order (or position). The output of CSAs are two vectors, namely, a sum and a carry, which when added together yield the final result. The benefit of a CSA is that high order bits have no dependency on any low order bit because all bit positions are calculated independently, thereby avoiding the propagation latency associated with carry bits in CPAs. Because of their speed and simplicity, CSAs are pervasively found in digital logic designs.
The present disclosure provides an improved CSA capable of simultaneously handling more inputs than any prior art CSA without only small increase in the required silicon area.
In accordance with a preferred embodiment of the present invention, a 6-to-3 carry-save adder includes a means for receiving six data inputs and a means for simultaneously adding the six data inputs to generate a first data output, a second data output, and a third data output. Preferably, the first data output is a SUM output, the second data output is a CARRY_2 output, and the third data output is a CARRY_4 output.
All features and advantages of the present invention will become apparent in the following detailed written description.